In the fields of the semiconductor memory techniques, competitive efforts have been carried out to increase the number of memory cells in a chip. In order to achieve the object, it is important to minimize the area of a memory cell array, on which a plurality of memory cells are formed within a restricted surface of a chip.
In realizing the minimum area of the memory cell, a DRAM (Dynamic Random Access Memory) in which an individual cell has a single transistor and a single capacitor is well known. Since a large portion of the area is occupied by the capacitor in the above-mentioned memory cell, with the development of higher packing density of the highly integrated semiconductor memory device, it becomes more important to increase the capacitance of the capacitor along with minimizing the ratio of the semiconductor area occupied by the capacitor, so as to facilitate the information detection and to decrease the soft errors resulting from alpha particles.
In order to minimize the area occupied by a capacitor and maximize the capacitance of a storage capacitor as described above, a spread stacked capacitor (to be called hereinafter SSC) cell structure, in which a storage electrode of each memory cell is expanded to the adjacent memory cell area, has been proposed. Such a conventional memory cell having the SSC cell structure was disclosed in pages 31 to 34 of IEDM 89.
In the prior art mentioned above, a first electrode of the capacitor expands to areas of adjacent memory cells by exposing the source region of each memory cell on a semiconductor silicon substrate in which transistors are formed. A 64Mbit DRAM can be achieved in the aforesaid structure of the SSC cell.
However, the prior art SSC cells structure is unable to obtain sufficient capacitive storage area required for a 256Mbit DRAM. The size of each first capacitor of the first memory cells is restricted by the size of each second capacitor of the second memory cells because the first capacitor is formed between the second capacitors. As a result, the size of the second capacitors are restricted to maintain balance with the size of the first capacitor. Accordingly, the second capacitors of the second memory cells can not fully expand to maximumly overlap the first capacitor of the first memory cells. Preferably, the size of the first capacitor should be enlarged to the size of the second capacitors, and the second capacitors of the second memory cells should be fully expanded to the first capacitor of the adjacent first memory cells. However, because the size of the first capacitor of the first memory cells is restricted by the second capacitor of the second memory cells in the conventional SSC cell structure, it is insufficient to obtain the effective area of the capacitor required for the 256 Mbit DRAM, wherein the cell size is smaller than that of the 64 Mbit DRAM.